1. Technical Field
The present invention relates in general to semiconductor devices and in particular to an improved semiconductor chip package. Still more particularly, the present invention relates to a semiconductor chip package having a silicon substrate with connection vias running through it for attaching and interconnecting to electrical power and other electronic devices.
2. Description of the Related Art
Due to an ever-increasing demand for performance and miniaturization, semiconductor manufacturers are continually driven to produce smaller and more efficient semiconductor devices. In order to reduce the size of semiconductor device packages, manufacturers have developed single and multi-chip modules (SCMs and MCMs) that efficiently house semiconductor chips having a large number of connections. A countervailing consideration in semiconductor device development is a desire to provide additional signal connections, and power connections for large power input to the semiconductor chips (also known as integrated circuit (IC) chips). A larger substrate is often required to accommodate these additional signal and power connections.
Traditionally, integrated circuit chips were placed on a ceramic substrate with connection points through the substrate. The chip pins were run through the substrate to provide connections. These ceramic substrates are easily drilled into a feature which allows connection signal wiring and power leads to be run through the substrate. However, with the increase in the number of chips on an individual substrate and the need for maximum chip density, utilization of ceramic substrate has become impractical. The ceramic substrate becomes rather expensive to manufacture because of the increased wiring required. Additionally, the additional wiring slowed the system down resulting in lower performance. Further, these packages did not perform well under thermal expansion as the substrate expanded at a different level than the silicon chips leading to breakage and other performance considerations.
Current multi-chip circuitry design requires attachment to a substrate of electrical and electronic devices, often times in the form of integrated circuit (IC) chips. The substrate which includes an interconnect wiring structure (or socket) and a support therefor, electrically connects the chips. Presently known attachments involve the attachment of the chips directly to the interconnect, thus forming a multilayer structure of support interconnect chips.
The interconnect surface serves a number of services in addition to chip attachment. For example, the interconnect surface provides for test pads for testing the attached circuitry and underlying wiring, for engineering changes pads for rewiring the circuitry, for termination resistors, for repair to the circuitry and so on. These different functions and their attendant structures compete with chip attachment structures for room on the interconnect. As a result, the chip packing density is less than optimal because space must be left between the chips for these other various structures. As more and more structure is required on the interconnect surface, the chip density declines. Optimally, the chip density should approach 100% in a planar multi-chip module.
Accordingly, there exists a need for a substrate structure which is capable of supporting the many functional requirements as required of such complex semiconductor chip structures while optimizing chip density.
New methods of semiconductor development involves the utilization of a silicon wafer as a substrate. Silicon substrate is cheaper and faster than ceramic substrate. The entire component is manufactured out of silicon and can be completed in the same process. Additionally, improved performance was achieved as the substrate now has the same thermal expansion as the IC chip. Consequently, silicon on silicon packaging has become more common and is quickly replacing multilayer ceramic packages.
The utilization of silicon wafer as substrate material is known in the art, particularly to solve the problem of matching the thermal coefficient of expansion between the substrate and the chips. U.S. Pat. No. 5,039,628 describes a multi-chip module wherein a silicon material can be utilized as a carrier for integrated circuit devices. A preferred carrier material will have a thermal coefficient of expansion to match the mounted chips.
Problems exist however in the utilization of silicon substrate. Unlike the ceramic substrate, silicon substrate is not easily bored. This means that wires can no longer be placed through the substrate. The connections are placed on the top surface of the substrate in a layer called the multilevel wiring. This has led to a new design for the entire semiconductor package with the wire connectors extending along the top of the substrate and off the sides. FIG. 1 depicts the new design being utilized for a typical silicon on silicon chip structure. Integrated circuit chips 103 are placed on silicon substrate 101 in a grid like pattern. At the edge of silicon substrate 101 are a number of metallic pads 109. These metallic pads 109 are utilized to provide off wafer connections to the chip, including power supply and electrical signals and ground. The silicon packages also utilize wire bond pads to receive input/output. Running below IC chip 103 in the top surface of silicon substrate 101 is a multilevel wiring (not shown) for connecting IC chips to provide on wafer processing.
As is obvious from FIG. 1 only the relatively small perimeter area of the substrate can be utilized to provide all the metallic pad connections required for the IC chip circuitry. This configuration limits the number of connection pads available to the IC chips, known in the art as "pad limited." Often this number is insufficient for the need of the IC chips during complex processing which require numerous external connections. Additionally, these connection pads and wiring structure do not allow for large power supplies to be provided to the chips which is oftentimes required. As can be ascertained, this severely hurts chip performance.
For purposes of reliability, the contacts for external connections cannot have very small dimensions and therefore a substantial part of the useful surface is occupied by these contacts. In addition, in the case of integrated circuits, a number of circuit elements must be connected together and to the external circuits. This results in multiple cross overs and super-positions and the connecting conductors which therefore must be mutually insulated by the interposition of dielectric layers. This construction causes an increase of fabrication costs, a reduction of the density of circuit elements which can be located on a single semiconductor wafer and a decrease in the production yield and in the reliability of the integrated circuit.
One method of correcting this limitation is to provide through wafer interconnects to the IC chips. With the connections placed below the wafer, the chip is then ideally able to connect as many leads as can fit on the bottom surface area of the wafer with minimum spacing between. Additionally, these leads can be made large enough to support huge power requirements.
Creating vias through the carrier material is known in the art. U.S. Pat. No. 4,956,695 is a three dimensional chip package wherein plural ICs, having interconnection leads extending therefrom are bonded with dielectric material. Ceramic spacers are placed between the leads and the ends of the spacers are then ground down to expose the interconnection leads. Ceramic spacers are used to match the thermal coefficient of expansion of the chips.
Other conventional systems utilize silicon as a carrier for integrated circuit devices and form vias in the silicon to allow connection through the carrier. For example, U.S. Pat. No. 3,787,252 is a semiconductor wafer having circuit elements formed on an epitaxial layer. Through connections are formed through the wafer to allow the circuit elements to contact interconnection points for conductors disposed on an adjacent insulating board. Although vias are created through the substrate, this patent utilizes these vias to connect an interlevel wiring located below the substrate with the chips at the top surface, resulting in longer chips and decreased efficiency. Further, the prior art does not allow for a large power supply because power connections are first fanned out at the wiring level before being sent through the larger conducting vias up to the chip.
U.S. Pat. No. 5,024,966 discusses a silicon substrate used to mount a semiconductor optical device. An external modulated current source is then interconnected to the optical device. The silicon substrate includes a metallized via to allow connection of the optical device to a conducting layer disposed on the opposite side of the substrate. U.S. Pat. No. 5,063,177 describes packaging of monolithic microwave integrated circuits on a motherboard of high resistivity silicon.
Substantial difficulties, increasing with the degree of miniaturization and the complexity of the circuits, are encountered in all these cases for establishing connection means. These difficulties are mainly caused by the fact that, in the prior art technique, the connection means comprise connecting contacts and conductors located exclusively on the same face of the conductor wafer on which the circuit elements are fabricated.
Prior art methods of creating the connections through the silicon have in large part been unsuccessful and/or inefficient. Currently two contrasting methods are utilized, dry etching and wet etching, both of which are well known in the art. Dry etching is an extremely slow process. It involves placing a photo resist on the substrate to cover places not desired etched, placing in a gas chamber and applying a plasma with gases to eat away at the exposed silicon. With this method, rapid etching of a silicon crystal is not possible. One of the faster dry etch techniques is covered in U.S. Pat. No. 4,741,799 by Chen and Matthad. This method yields an etch rate of 1.6 microns per minute. At this rate with a typical wafer being about 2 millimeters, dry etch of a single substrate would take almost a day to complete.
The second process, wet etch is relatively quicker than dry etch. However, wet etching occurs in a preferential direction usually at an angle of about 107 degrees. It etches at a fixed angle along a crystal plane. That means that with a 1 millimeter via, the depth will not reach the other side of a wafer. Thus this technique though faster, utilize a large surface area for each via resulting in a loss of chip surface area for additional connection points similar to the problem with the current chips with side connectors.
Central processing units need high power to feed the integrated circuits populated on the package. Current silicon on silicon packaging schemes utilize wiring bonding to get signals off the silicon substrate. The wire bonding cannot be utilized for the high power needed. Large vias through the substrate will be reliable carriers of the power needed.. The high power problem has not been addressed in the silicon on silicon scheme.
It is therefore desirable to have a substrate design for a semiconductor chip package which provides the signal and power connections necessary for efficient processing. It is further desirable to provide a package with a via having a constant bore to maximize utilization of the surface area for increased density of connections to IC chips on a silicon substrate.